Queue Management in Network Processors

TL;DR

This paper analyzes memory management bottlenecks in network processors, highlighting the limitations of software solutions and proposing a hardware memory manager that achieves high throughput for multiple queues.

Contribution

It introduces a hardware memory manager architecture that overcomes software limitations, enabling wire-speed processing with support for thousands of queues.

Findings

Hardware memory manager achieves up to 6.2Gbps throughput

Supports 32K independent queues efficiently

Identifies hardware assistance as essential for gigabit speeds

Abstract

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performance bottlenecks of various data memory managers integrated in typical Network Processing Units (NPUs). We expose the performance limitations of software implementations utilizing the RISC processing cores typically found in most NPU architectures and we identify the requirements for hardware assisted memory management in order to achieve wire-speed operation at gigabit per second rates. Furthermore, we describe the architecture and performance of a hardware memory manager that fulfills those requirements. This memory manager, although it is implemented in a reconfigurable technology, it can provide up to 6.2Gbps of aggregate throughput, while handling 32K independent queues.