Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures

TL;DR

This paper analyzes the trade-offs between area, power, and throughput in FPGA implementations of pipelined discrete wavelet transform architectures using the lifting scheme, highlighting the benefits of pipelined and behavioral HDL designs.

Contribution

It provides a comparative study of five FPGA implementations of DWT, demonstrating that pipelined and behavioral HDL designs optimize area, power, and frequency trade-offs.

Findings

Pipelined operators offer better area-power-frequency trade-offs.

Pipelined designs increase maximum frequency by up to 100%.

Behavioral HDL descriptions improve hardware cost and frequency by 30%.

Abstract

The JPEG2000 standard defines the discrete wavelet transform (DWT) as a linear space-to-frequency transform of the image domain in an irreversible compression. This irreversible discrete wavelet transform is implemented by FIR filter using 9/7 Daubechies coefficients or a lifting scheme of factorizated coefficients from 9/7 Daubechies coefficients. This work investigates the tradeoffs between area, power and data throughput (or operating frequency) of several implementations of the Discrete Wavelet Transform using the lifting scheme in various pipeline designs. This paper shows the results of five different architectures synthesized and simulated in FPGAs. It concludes that the descriptions with pipelined operators provide the best area-power-operating frequency trade-off over non-pipelined operators descriptions. Those descriptions require around 40% more hardware to increase the maximum operating frequency up to 100% and reduce power consumption to less than 50%. Starting from behavioral HDL descriptions provide the best area-power-operating frequency trade-off, improving hardware cost and maximum operating frequency around 30% in comparison to structural descriptions for the same power requirement.