Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method

TL;DR

This paper presents a hardware accelerator for elliptic curve cryptography that uses an iterative Karatsuba method to significantly reduce area and energy consumption, making it suitable for resource-constrained wireless devices.

Contribution

It introduces an iterative application of Karatsuba's method for polynomial multiplication in hardware, optimizing area and energy use over traditional recursive approaches.

Findings

Area reduced to 2.1 mm^2 from 6.2 mm^2

Energy consumption decreased by 40%

Execution time increased but remains acceptable

Abstract

Securing communication channels is especially needed in wireless environments. But applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices. If hardware is applied to realize cryptographic operations cost becomes an issue. In this paper we describe an approach which tackles all these three points. We implemented a hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba's method iteratively. With this approach the area consumption is reduced to 2.1 mm^2 in comparison to. 6.2 mm^2 for the standard application of Karatsuba's method i.e. for recursive application. Our approach also reduces the energy consumption to 60 per cent of the original approach. The price we have to pay for these achievement is the increased execution time. In our implementation a polynomial multiplication takes 3 clock cycles whereas the recurisve Karatsuba approach needs only one clock cycle. But considering area, energy and calculation speed we are convinced that the benefits of our approach outweigh its drawback.