Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

TL;DR

This paper presents a transaction-level model of an extended AMBA2.0 bus architecture that achieves significantly faster simulation speeds while maintaining high accuracy, aiding large-scale SoC performance analysis.

Contribution

The paper introduces a novel TLM of the AHB+ bus supporting extended AMBA2.0, demonstrating a 353x speedup with 97% accuracy, and details its development process.

Findings

353 times faster than RTL models

Maintains 97% accuracy on average

Facilitates large-scale SoC performance analysis

Abstract

Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while maintaining 97% of accuracy on average. We also present the development procedure of TLM of a bus architecture.