A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

TL;DR

This paper introduces a VLSI design flow that integrates security features to produce ICs resistant to side-channel attacks, enabling secure hardware design without extensive custom layouts or simulations.

Contribution

It proposes a practical design flow that modifies standard CMOS processes for enhanced security against side-channel attacks, simplifying secure IC development.

Findings

Secure version withstands over 2000 measurements in DPA attack

Regular CMOS design can be adapted for security with minimal modifications

Experimental results demonstrate effective side-channel attack resistance

Abstract

This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.