Hardware Engines for Bus Encryption: A Survey of Existing Techniques

TL;DR

This survey reviews existing hardware-based bus encryption techniques for embedded systems, discussing their security benefits and the performance overheads involved in securing processor-memory communications.

Contribution

It provides a comprehensive overview of current hardware engine techniques for bus encryption and analyzes their performance implications in embedded device security.

Findings

Most techniques introduce significant performance overheads.

Hardware solutions vary in complexity and security level.

Trade-offs exist between security strength and system performance.

Abstract

The widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security. Most of those embedded systems (pay-TV, PDAs, mobile phones, etc...) make use of external memory. As a result, the main problem is that data and instructions are constantly exchanged between memory (RAM) and CPU in clear form on the bus. This memory may contain confidential data like commercial software or private contents, which either the end-user or the content provider is willing to protect. The goal of this paper is to clearly describe the problem of processor-memory bus communications in this regard and the existing techniques applied to secure the communication channel through encryption - Performance overheads implied by those solutions will be extensively discussed in this paper.