An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security

TL;DR

This paper presents an improved FPGA micro-architecture for the hybrid hiding encryption algorithm, enhancing parallel processing and security, with detailed simulation, implementation results, and comparative analysis.

Contribution

It introduces a modified FPGA micro-architecture that overcomes previous limitations by enabling parallel bit replacement and reducing key-dependent vulnerabilities.

Findings

Enhanced throughput due to parallel bit replacement

Reduced security vulnerability from key dependency

Successful implementation with detailed performance analysis

Abstract

The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement, and the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules. These modules are; the message cache, the message alignment module, the key cache, the comparator, and at last the encryption module. In this work, we provide comprehensive simulation and implementation results. These are: the timing diagrams, the post-implementation timing and routing reports, and finally the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed.