Rapid Generation of Thermal-Safe Test Schedules

TL;DR

This paper introduces a thermal-aware test scheduling method for complex SOCs that quickly generates safer test schedules by using a low-complexity thermal model, reducing overheating risks without extensive simulations.

Contribution

It presents a novel thermal-aware test scheduling approach that incorporates a simple thermal model to prevent overheating during testing, improving upon existing power-constrained methods.

Findings

Reduces overheating during SOC testing

Avoids time-consuming thermal simulations

Decreases likelihood of design re-spins

Abstract

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.