A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
Javier Resano, Daniel Mozos, Francky Catthoor

TL;DR
This paper presents a hybrid prefetch scheduling heuristic for dynamically reconfigurable hardware that reduces run-time reconfiguration overhead by precomputing near-optimal schedules during design-time.
Contribution
It introduces a novel hybrid approach combining design-time computation with run-time scheduling to minimize reconfiguration overhead in DRHW systems.
Findings
Significantly reduces run-time reconfiguration overhead
Maintains high flexibility with negligible penalty
Precomputes near-optimal schedules during design-time
Abstract
Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable Hardware (DRHW) is a promising candidate to provide this flexibility but, currently, not sufficient run-time scheduling support to deal with the run-time reconfigurations exists. Moreover, executing at run-time a complex scheduling heuristic to provide this support may generate an excessive run-time penalty. Hence, we have developed a hybrid design/run-time prefetch heuristic that schedules the reconfigurations at run-time, but carries out the scheduling computations at design-time by carefully identifying a set of near-optimal schedules that can be selected at run-time. This approach provides run-time flexibility with a negligible penalty.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsEmbedded Systems Design Techniques · Real-Time Systems Scheduling · Parallel Computing and Optimization Techniques
