Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage

TL;DR

This paper explores how different threshold voltages and oxide thicknesses affect power and performance trade-offs in nanometer-scale multi-level caches, proposing strategies for leakage reduction and cache sizing.

Contribution

It introduces a comprehensive analysis of Vth and T_{ox} variations in multi-level caches, highlighting design choices for leakage minimization and cache configuration.

Findings

Increasing L2 size can reduce power with a single Vth/T_{ox} pair.

Multiple Vth and T_{ox} settings can minimize total leakage.

Vth is more effective than T_{ox} for leakage optimization.

Abstract

In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expanded as a result of cache misses. Our results show that one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of Vth/T_{ox} in L2. However, if we allow the memory cells and the peripherals to have their own Vth's and T_{ox}'s, we show that a two-level cache system with smaller L2's will yield less total leakage. We further show that two Vth's and two T_{ox}'s are sufficient to get close to an optimal solution, and that Vth is generally a better design knob than T_{ox} for leakage optimization, thus it is better to restrict the number of T_{ox}'s rather than Vth's if cost is a concern.