Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

TL;DR

This paper presents a detailed logic design for on-chip high-speed clock generation to improve delay testing of SOC devices, reducing test costs and enhancing test quality.

Contribution

It introduces novel on-chip clock generation techniques that lower test vector count and improve delay test accuracy, supported by ATPG results.

Findings

Reduced test vector count in delay testing

Improved test quality for high-frequency SOCs

Validated techniques with ATPG results

Abstract

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.