Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

TL;DR

This paper introduces an optimized design methodology for selective multi-threshold CMOS circuits that reduces standby leakage power by enabling multiple MT-cells to share a switch transistor, from RTL to layout.

Contribution

It presents a novel design flow that allows multiple MT-cells to share a switch transistor, improving efficiency in leakage power reduction.

Findings

Shared switch transistors reduce area and power consumption.

Design methodology from RTL to layout enhances leakage reduction.

Improved selective-MT circuit performance in standby mode.

Abstract

This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.