Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

TL;DR

This paper presents low-cost, high-performance testing systems for multi-gigahertz signals using CMOS FPGAs and PECL, enabling affordable yet accurate device testing at 2-5 Gbps.

Contribution

It introduces two innovative testing techniques that leverage commercially available components to achieve high-speed performance at reduced costs.

Findings

Achieved 2-5 Gbps testing with low-cost components

Demonstrated performance comparable to expensive ATE systems

Provided flexible FPGA-based control and high-speed data handling

Abstract

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\pm$25ps timing accuracy.