Low Power Oriented CMOS Circuit Optimization Protocol

TL;DR

This paper presents a CMOS circuit optimization protocol that uses a closed-form delay model to efficiently select the best design modifications for minimal area cost under delay constraints, validated on benchmarks.

Contribution

It introduces a deterministic, closed-form model-based optimization protocol for CMOS circuit design that balances delay constraints with minimal area, improving upon existing methods.

Findings

Achieves comparable optimization efficiency to industrial tools

Validates the method on ISCAS'85 benchmarks

Demonstrates effective trade-off management between performance and structure

Abstract

Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternative. The target is delay constraint satisfaction with minimum area cost. We validate the design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. An optimisation protocol is finally defined to manage the trade-off performance constraint - circuit structure. These methods are implemented in an optimization tool (POPS) and validated by comparing on a 0.25$\mu$m process, the optimization efficiency obtained on various benchmarks (ISCAS?85) to that resulting from an industrial tool.