A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

TL;DR

This paper introduces a fast, analytical power-thermal modeling approach for sub-100nm digital ICs, enabling rapid and accurate estimation of static power and temperature without complex numerical calculations.

Contribution

It presents novel compact models for static power and temperature estimation that are faster and more efficient than existing numerical methods.

Findings

Models show excellent agreement with measurements and SPICE simulations.

The approach significantly reduces computation time for power-thermal analysis.

Applicable to 0.12mm technology nodes and beyond.

Abstract

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results.