Techniques for Fast Transient Fault Grading Based on Autonomous Emulation

TL;DR

This paper introduces a new FPGA-based emulation system for fast transient fault grading, significantly reducing evaluation time for soft errors caused by radiation in advanced IC technologies.

Contribution

It presents a novel FPGA emulation approach that performs all fault evaluation internally, eliminating communication bottlenecks and accelerating soft error assessment.

Findings

Achieves faster fault grading compared to traditional methods

Reduces evaluation time by performing all processes within FPGA

Demonstrates effectiveness in soft error assessment for advanced ICs

Abstract

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in many applications where Fault Tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the FT evaluation. In this work, a new emulation system for FT evaluation with respect to SEU effects is proposed, providing shorter evaluation times by performing all the evaluation process in the FPGA and avoiding emulator-host communication bottlenecks.