Design Method for Constant Power Consumption of Differential Logic Circuits

TL;DR

This paper introduces a design methodology for fully connected differential pull-down networks in logic gates, ensuring constant power consumption to mitigate side channel attacks in security ICs.

Contribution

It proposes a novel design approach for differential networks that maintain constant power dissipation regardless of input signals, enhancing security against power analysis attacks.

Findings

Design of fully connected differential pull-down networks

Achieves constant power consumption in logic gates

Applicable to security ICs to prevent side channel attacks

Abstract

Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals, are used in security ICs. This paper presents a design methodology to create fully connected differential pull down networks. Fully connected differential pull down networks are transistor networks that for any complementary input combination connect all the internal nodes of the network to one of the external nodes of the network. They are memoryless and for that reason have a constant load capacitance and power consumption. This type of networks is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate.