A New Embedded Measurement Structure for eDRAM Capacitor

TL;DR

This paper introduces a novel embedded measurement structure for eDRAM capacitors, enabling precise capacitance measurement of individual cells within an array, validated through simulation for improved process monitoring.

Contribution

The paper presents a new test structure specifically designed for measuring eDRAM capacitor values at the cell level, addressing challenges in process monitoring and failure analysis.

Findings

Validated by simulation on 0.18μm eDRAM technology

Enables precise measurement of individual capacitor values

Addresses process monitoring challenges in eDRAM fabrication

Abstract

The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The integration of the DRAM capacitor process into a logic process is challenging to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (~30F) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18$\mu$m eDRAM technology.