Leakage-Aware Interconnect for On-Chip Network

TL;DR

This paper introduces four leakage-aware interconnect schemes for on-chip networks, significantly reducing power consumption with minimal delay increase, thus enhancing energy efficiency in future multi-core systems.

Contribution

It proposes four novel leakage-aware interconnect schemes that effectively reduce both active and standby leakage power in on-chip networks.

Findings

Active leakage savings of up to 63.57%

Standby leakage savings of up to 95.96%

Delay penalty is limited to 4.69%

Abstract

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.