Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

TL;DR

This paper investigates how loading effects influence leakage power in nano-scaled CMOS logic circuits and proposes a method to accurately estimate total leakage considering circuit topology and device interactions.

Contribution

It introduces a novel analysis of loading effects on leakage and presents a method for precise leakage estimation from logic-level descriptions.

Findings

Loading effects significantly impact leakage power in nano-CMOS circuits.

The proposed method accurately estimates total leakage considering circuit topology.

Leakage components interact at device and circuit levels, affecting overall power.

Abstract

In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power in a logic circuit. Leakage components interact with each other in device level (through device geometry, doping profile) and also in the circuit level (through node voltages). Due to the circuit level interaction of the different leakage components, the leakage of a logic gate strongly depends on the circuit topology i.e. number and nature of the other logic gates connected to its input and output. In this paper, for the first time, we have analyzed loading effect on leakage and proposed a method to accurately estimate the total leakage in a logic circuit, from its logic level description considering the impact of loading and transistor stacking.