Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

TL;DR

This paper details a comprehensive top-down approach for designing a low-power, multi-channel clock recovery circuit using gated oscillators, achieving significant power efficiency and verified through extensive simulation and modeling.

Contribution

It introduces a novel top-down design methodology for a low-power multi-channel clock recovery circuit with detailed verification and practical implementation examples.

Findings

Power consumption as low as 5mW/Gbit/s

Feasibility confirmed through statistical simulation

Design validated with VHDL modeling and thermal noise analysis

Abstract

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two practical examples of possible design improvements analyzed and implemented with this methodology.