Systematic Figure of Merit Computation for the Design of Pipeline ADC
L. Barrandon (IETR), S. Crand (IETR), D. Houzet (IETR)

TL;DR
This paper introduces a systematic method for evaluating pipeline ADC configurations using a figure of merit, enabling efficient high-level optimization without extensive simulations.
Contribution
It develops a top-down approach for pipeline ADC design that compares configurations based on imperfections and architecture, bypassing complex simulations.
Findings
Provides a new figure of merit for ADC configuration comparison
Enables faster optimization of pipeline ADCs
Reduces reliance on time-consuming simulations
Abstract
The emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a given technology, it consists in comparing different configurations according to their imperfections and their architectures without FFT computation or time-consuming simulations. The final selection is based on a figure of merit.
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Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · Analog and Mixed-Signal Circuit Design
