Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

TL;DR

This paper introduces a hybrid design methodology combining analytical and simulation models to optimize pipelined ADCs, demonstrating power minimization through stage-resolution adjustment for a 13-bit, 40 MSPS converter.

Contribution

It presents a novel hybrid synthesis approach that integrates designer insights with circuit simulations to optimize ADC power efficiency.

Findings

Optimal stage-resolution distribution identified as 4-3-2 for lowest power consumption.

Power-efficient design achieved for a 13-bit, 40 MSPS pipelined ADC.

Hybrid methodology effectively guides ADC configuration exploration.

Abstract

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 $\mu$m CMOS process.