Specification Test Compaction for Analog Circuits and MEMS

TL;DR

This paper introduces an e-SVM based statistical learning method to reduce redundant tests in analog and MEMS device testing, significantly lowering costs while maintaining high defect detection accuracy.

Contribution

It presents a novel application of e-SVM for test compaction, effectively identifying redundant specification tests with minimal defect escape and yield loss.

Findings

Redundant tests can be eliminated with less than 1% defect escape.

Test cost for MEMS accelerometers can be halved.

Method maintains high testing accuracy after test reduction.

Abstract

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing e-SVM based statistical learning. Application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests with negligible error. Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer, defect escape of 0.2% and yield loss of 0.1% occurs when the hot and colt tests are eliminated. For the accelerometer, this level of Compaction would reduce test cost by more than half.