Optimized Generation of Data-Path from C Codes for FPGAs

TL;DR

This paper presents ROCCC, a compiler that translates C code into FPGA circuits, focusing on data path generation, and compares its performance to Xilinx IPs, showing comparable clock rates with larger area.

Contribution

It introduces an improved data path generation method in ROCCC for translating C code into FPGA circuits, enhancing high-level language programmability for FPGAs.

Findings

ROCCC-generated circuits have 2x to 3x larger area than Xilinx IPs.

ROCCC circuits achieve comparable clock rates to Xilinx IPs.

The approach improves high-level FPGA programming from C source code.

Abstract

FPGAs, as computing devices, offer significant speedup over microprocessors. Furthermore, their configurability offers an advantage over traditional ASICs. However, they do not yet enjoy high-level language programmability, as microprocessors do. This has become the main obstacle for their wider acceptance by application designers. ROCCC is a compiler designed to generate circuits from C source code to execute on FPGAs, more specifically on CSoCs. It generates RTL level HDLs from frequently executing kernels in an application. In this paper, we describe ROCCC's system overview and focus on its data path generation. We compare the performance of ROCCC-generated VHDL code with that of Xilinx IPs. The synthesis result shows that ROCCC-generated circuit takes around 2x ~ 3x area and runs at comparable clock rate.