Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

TL;DR

This paper develops a circuit-level model for gate oxide breakdown defects, identifying specific test patterns to detect such faults, and demonstrates how to propagate these patterns for effective testing of integrated circuits.

Contribution

It introduces a novel model for operational OBD defects and proposes a method to generate and propagate test patterns for their detection at the circuit level.

Findings

Traditional pattern generators fail to exercise all OBD defects.

Test patterns can be propagated and justified for combinational circuits.

The model enables more effective testing of OBD-related faults.

Abstract

As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational OBD defects, and we explore how to test for faults due to OBD. For a NAND gate, we derive the necessary input conditions that excite and detect errors due to OBD defects at the gate level. We show that traditional pattern generators fail to exercise all of these defects. Finally, we show that these test patterns can be propagated and justified for a combinational circuit in a manner similar to traditional ATPG.