Assertion-Based Design Exploration of DVS in Network Processor Architectures

TL;DR

This paper presents an assertion-based methodology for analyzing power and performance trade-offs in network processors using dynamic voltage scaling techniques, enabling efficient exploration of design configurations.

Contribution

It introduces an assertion-based system-level analysis approach for DVS in network processors, facilitating optimal configuration selection.

Findings

Traffic-based DVS reduces power consumption with acceptable performance loss.

Execution-based DVS offers better performance-power trade-offs under certain conditions.

The methodology efficiently compares multiple DVS configurations in large design spaces.

Abstract

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.