Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

TL;DR

This paper presents a statistical gate sizing method to improve process-variation tolerance in digital circuits, significantly reducing performance variance with manageable area increase.

Contribution

It introduces a novel optimization framework using statistical critical paths and a new max operation approximation for variance reduction.

Findings

72% average reduction in performance variation

20% average increase in design area

Effective gate sizing strategy for process variation mitigation

Abstract

A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72% reduction in performance variation at the expense of average 20% increase in design area.