FPGA Architecture for Multi-Style Asynchronous Logic

TL;DR

This paper introduces a flexible FPGA architecture designed to support multiple styles of asynchronous logic, enabling adaptability and evolution in asynchronous circuit implementation.

Contribution

It presents a novel, generic FPGA architecture that can be adapted to various asynchronous logic styles, enhancing flexibility and future-proofing.

Findings

Full-adder implemented in different logic styles demonstrates architecture flexibility.

Architecture supports multiple asynchronous logic styles without dependency.

Design shows potential for future asynchronous logic evolutions.

Abstract

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.