Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

TL;DR

This paper discusses the challenges and design issues faced when implementing analog and digital circuits in 65 nm CMOS technology, including power, variability, and signal integrity, and debates whether this technology node marks the end of scaling.

Contribution

It provides an overview of key design problems in 65 nm CMOS and includes expert opinions on the future of technology scaling beyond 65 nm.

Findings

Identification of main challenges like leakage power and variability

Discussion on the implications of reduced supply voltages

Expert opinions on the continuation of technology scaling

Abstract

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.