An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

TL;DR

This paper introduces an infrastructure for testing FPGA architectures generated by high-level compilers, enabling verification of compiler outputs after optimizations or modifications through functional simulation.

Contribution

It provides a novel testing infrastructure that verifies FPGA architectures produced by compilers, supporting ongoing compiler development and optimization validation.

Findings

Enables functional verification of FPGA architectures

Supports iterative testing after compiler optimizations

Facilitates research in FPGA compilation techniques

Abstract

This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.