A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
Roman Lysecky, Frank Vahid

TL;DR
This paper investigates dynamic hardware/software partitioning to enhance FPGA soft processor cores, demonstrating significant speedups and energy savings, making soft cores more competitive with hard-core processors for various applications.
Contribution
It introduces a warp processing technique for soft-core processors that improves performance and energy efficiency through dynamic re-implementation of critical kernels.
Findings
Average speedup of 5.8 times over soft core
Energy consumption reduced by 57%
Performance comparable to hard-core processors
Abstract
Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate…
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and FPGA Design Techniques · Parallel Computing and Optimization Techniques
