Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

TL;DR

This paper proposes a domain-specific reconfigurable array architecture that shares resources and pipelines functional units to reduce hardware cost and latency without sacrificing performance.

Contribution

It introduces a new architecture template and design flow for optimizing coarse-grained reconfigurable architectures for specific application domains.

Findings

Significant reduction in hardware resources compared to existing architectures

Improved performance and area efficiency demonstrated through experiments

Effective resource sharing and pipelining strategies for domain-specific applications

Abstract

Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such reconfigurable array architecture template and design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient both in performance and area compared to existing reconfigurable architectures.