Memory Testing Under Different Stress Conditions: An Industrial Evaluation

TL;DR

This paper evaluates the effectiveness of various stress testing conditions, such as voltage and frequency, in detecting defects in deep sub-micron embedded memories within an industrial setting, aiming to improve product quality and reduce defect rates.

Contribution

It introduces a comprehensive validation of stress testing conditions on real silicon, utilizing IFA-based simulation for efficient fault coverage and defect estimation.

Findings

Stress conditions improve defect detection in embedded memories.

Validation on real silicon confirms simulation results.

Stress testing reduces defect-per-million levels.

Abstract

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 um technology. IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.