RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power

TL;DR

This paper introduces a hybrid repeater insertion algorithm that combines analytical and dynamic programming techniques to significantly reduce interconnect power consumption efficiently.

Contribution

It presents a novel hybrid approach that improves power savings and computational speed over existing repeater insertion methods.

Findings

Achieves up to 37% higher power savings compared to previous schemes.

Attains a speedup of two orders of magnitude for the same design quality.

Effectively balances solution quality and runtime efficiency.

Abstract

This paper presents a novel repeater insertion algorithm for interconnect power minimization. The novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method. Specifically, the analytical solver chooses a concise repeater library and a small set of repeater location candidates such that the dynamic programming algorithm can be performed fast with little degradation of the solution quality. In comparison with previously reported repeater insertion schemes, within comparable runtimes, our approach achieves up to 37% higher power savings. Moreover, for the same design quality, our scheme attains a speedup of two orders of magnitude.