On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips

TL;DR

This paper proposes an on-chip design for test infrastructure that optimizes multi-site testing throughput of system chips by integrating DfT features, reducing the need for extensive ATE resources.

Contribution

It introduces an on-chip DfT design, including wrappers and TAMs, optimized for maximum test throughput under given ATE constraints.

Findings

Achieved increased test throughput for Philips SOC

Demonstrated effectiveness on ITC'02 benchmarks

Reduced ATE resource requirements

Abstract

Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.