SOC Testing Methodology and Practice

TL;DR

This paper presents a comprehensive SOC testing methodology that integrates various testing techniques to reduce costs, test time, and area overhead, validated on a commercial DSC controller chip.

Contribution

It introduces a novel SOC test integration platform with practical solutions for test scheduling, IO reduction, BIST, and sharing, demonstrated through successful chip fabrication and testing.

Findings

Achieved short test integration cost and time

Reduced test IO and area overhead

Validated approach on a commercial DSC chip

Abstract

On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results justify that short test integration cost, short test time, and small area overhead can be achieved. To support SOC testing, a memory BIST compiler and an SOC testing integration system have been developed.