Integration, Verification and Layout of a Complex Multimedia SOC

TL;DR

This paper shares the comprehensive process and collaborative efforts involved in designing a complex multimedia system-on-chip for digital cameras, highlighting challenges, solutions, and lessons learned from specification to mass production.

Contribution

It details the integration, verification, and layout processes of a complex multimedia SOC, including collaboration with various industry and academic partners, and development of testing methodologies.

Findings

Successful integration of a multimedia SOC for digital cameras

Development of JPEG codec IP and memory BIST methodologies

Lessons learned in collaborative SOC design process

Abstract

We present our experience of designing a single-chip controller for advanced digital still camera from specification all the way to mass production. The process involves collaboration with camera system designer, IP vendors, EDA vendors, silicon wafer foundry, package and testing houses, and camera maker. We also co-work with academic research groups to develop a JPEG codec IP and memory BIST and SOC testing methodology. In this presentation, we cover the problems encountered, our solutions, and lessons learned.