Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

TL;DR

This paper develops statistical models to estimate pipeline yield under process variation in sub-100nm technologies and proposes an optimal design methodology to improve yield by stage delay imbalance.

Contribution

It introduces analytical models for pipeline delay distribution and a statistical design methodology to enhance yield through stage delay imbalance.

Findings

Imbalance among stage delays improves yield by 9%.

Proper design reduces area by 8.4% under yield constraints.

Models accurately predict yield considering process variation.

Abstract

Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design.