Synchronization Processor Synthesis for Latency Insensitive Systems

TL;DR

This paper introduces a synchronization processor for latency insensitive systems that optimizes IP encapsulation to improve speed, reduce silicon area, and ensure synthesizability in SoC designs.

Contribution

It presents a new wrapper model for IP encapsulation that maintains IP performance and optimizes area and speed in latency insensitive systems.

Findings

Optimized wrapper model improves IP performance preservation.

Reduces silicon area in SoC designs.

Ensures synthesizability of encapsulated IP.

Abstract

In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them and reduce SoC silicon area.