Simultaneous Reduction of Dynamic and Static Power in Scan Structures

TL;DR

This paper introduces a technique to simultaneously reduce dynamic and static power in scan structures of integrated circuits by multiplexing non-critical scan cell outputs and optimizing input vectors, proven effective on benchmark circuits.

Contribution

It proposes a novel method to minimize both dynamic and static power in scan testing, including a vector selection technique for power reduction.

Findings

Significant power savings demonstrated on ISCAS89 benchmarks

Effective reduction of leakage current during scan mode

Technique applicable to future low-power IC designs

Abstract

Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. This paper proposes an efficient technique to reduce both dynamic and static power dissipation in scan structures. Scan cell outputs which are not on the critical path(s) are multiplexed to fixed values during scan mode. These constant values and primary inputs are selected such that the transitions occurred on non-multiplexed scan cells are suppressed and the leakage current during scan mode is decreased. A method for finding these vectors is also proposed. Effectiveness of this technique is proved by experiments performed on ISCAS89 benchmark circuits.