At-Speed Logic BIST for IP Cores

TL;DR

This paper presents a flexible at-speed logic BIST scheme for IP cores that achieves high fault coverage, supports multi-clock designs without frequency changes, and is easy to implement physically.

Contribution

It introduces a novel at-speed logic BIST method with fault-simulation guided test point insertion and low-speed SE signals for practical application.

Findings

High fault coverage achieved in IP cores

Supports multi-clock designs without frequency manipulation

Easy physical implementation due to low-speed SE signal

Abstract

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.