Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

TL;DR

This paper introduces the RCPN model, a simplified yet powerful approach for modeling pipelined processors that enables the rapid generation of high-performance cycle-accurate simulators, significantly outperforming existing tools.

Contribution

The paper presents the RCPN model, combining simplicity and efficiency to facilitate intuitive processor modeling and fast simulator generation, addressing limitations of previous methods.

Findings

Achieved ~15x speedup over SimpleScalar ARM simulator

RCPN models are intuitive and mirror processor pipeline diagrams

Successfully generated high-performance simulators for XScale and StrongArm

Abstract

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.