The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
Irith Pomeranz, Sudhakar M. Reddy

TL;DR
This paper introduces the accidental detection index heuristic for fault ordering in full-scan circuits, improving test set compactness and fault coverage efficiency through a novel fault prioritization method.
Contribution
It proposes a new fault ordering heuristic based on the accidental detection index, enhancing test generation for full-scan circuits.
Findings
Heuristic leads to more compact test sets.
Test sets have steeper fault coverage curves.
Experimental results confirm heuristic effectiveness.
Abstract
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI (f) with every circuit fault f. The heuristic estimates the number of faults that will be detected by a test generated for f. Fault ordering is done such that a fault with a higher accidental detection index appears earlier in the ordered fault set and targeted earlier during test generation. This order is effective for generating compact test sets, and for obtaining a test set with a steep fault coverage curve. Such a test set has several applications. We present experimental results to demonstrate the effectiveness of the heuristic.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Physical Unclonable Functions (PUFs) and Hardware Security
