A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching

TL;DR

This paper introduces a probabilistic collocation method-based statistical gate delay model that accounts for process variations and multiple input switching, achieving high accuracy in delay prediction.

Contribution

It presents a novel delay modeling approach using orthogonal polynomial probabilistic collocation to accurately capture process variations and input switching effects.

Findings

Less than 0.2% error on mean delay

Less than 3% error on delay standard deviation

Effective modeling of process variations and input switching

Abstract

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.