DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

TL;DR

This paper presents a formal approach to designing quasi delay insensitive asynchronous circuits resistant to differential power analysis, including modeling, leakage identification, and a flow to minimize information leakage, validated on an AES processor.

Contribution

It introduces a formal modeling framework and a complete design flow to enhance DPA resistance in QDI asynchronous circuits, validated through a practical AES implementation.

Findings

Formal model of electrical signatures for QDI circuits

Effective identification of leakage sources using DPA

Design flow reduces information leakage in AES processor

Abstract

The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.