Unit Rectangle Visibility Graphs

TL;DR

This paper investigates unit rectangle visibility graphs (URVGs), where vertices are fixed-size squares in the plane, and establishes conditions for certain graph classes to be URVGs, relevant for VLSI chip design.

Contribution

It provides necessary and sufficient conditions for complete graphs, bipartite graphs, and trees to be URVGs, along with general edge bounds, advancing understanding of constrained geometric graph representations.

Findings

Characterization of URVGs for complete graphs and bipartite graphs.

Conditions for trees to be URVGs.

Bounds on the number of edges in URVGs.

Abstract

Over the past twenty years, rectangle visibility graphs have generated considerable interest, in part due to their applicability to VLSI chip design. Here we study unit rectangle visibility graphs, with fixed dimension restrictions more closely modeling the constrained dimensions of gates and other circuit components in computer chip applications. A graph $G$ is a unit rectangle visibility graph (URVG) if its vertices can be represented by closed unit squares in the plane with sides parallel to the axes and pairwise disjoint interiors, in such a way that two vertices are adjacent if and only if there is a non-degenerate horizontal or vertical band of visibility joining the two rectangles. Our results include necessary and sufficient conditions for $K_n$, $K_{m,n}$, and trees to be URVGs, as well as a number of general edge bounds.