On Frequency Optimisation for Power Saving in WSNs: Finding Optimum Hardware Timers Frequencies

TL;DR

This paper investigates optimal frequency scaling for power saving in wireless sensor networks, analyzing hardware constraints and proposing a configuration management tool for microcontroller optimization.

Contribution

It introduces a method to determine optimal timer frequencies considering various constraints and provides a tool to aid application-specific microcontroller configuration.

Findings

Identified relationships between clock frequencies and microcontroller constraints.

Developed a configuration management tool for power-efficient microcontroller setup.

Enhanced understanding of frequency scaling impacts on power consumption.

Abstract

Wireless Sensor Networks research and demand are now in full expansion, since people came to understand these are the key to a large number of issues in industry, commerce, home automation, healthcare, agriculture and environment, monitoring, public safety etc. One of the most challenging research problems in sensor networks research is power awareness and power-saving techniques. In this master's thesis, we have studied one particular power-saving technique, i.e. frequency scaling. In particular, we analysed the close relationship between clock frequencies in a microcontroller and several types of constraints imposed on these frequencies, e.g. by other components of the microcontroller, by protocol specifications, by external factors etc. Among these constraints, we were especially interested in the ones imposed by the timer service and by the serial ports' transmission rates. Our efforts resulted in a microcontroller configuration management tool which aims at assisting application programmers in choosing microcontroller configurations, in function of the particular needs and constraints of their application.