Thermal measurement and modeling of multi-die packages

TL;DR

This paper investigates thermal measurement and modeling techniques for multi-die packages with mixed arrangements, focusing on an opto-coupler device, and introduces methods for validating models and deriving thermal resistances.

Contribution

It presents a comprehensive overview of measurement and modeling techniques for stacked and MCM structures, including a novel validation methodology and junction-to-pin resistance derivation.

Findings

Validated detailed thermal models against measurements

Demonstrated structure function-based validation approach

Derived junction-to-pin thermal resistances using structure functions

Abstract

Thermal measurement and modeling of multi-die packages became a hot topic recently in different fields like RAM chip packaging or LEDs / LED assemblies, resulting in vertical (stacked) and lateral arrangement. In our present study we show results for a mixed arrangement: an opto-coupler device has been investigated with 4 chips in lateral as well as vertical arrangement. In this paper we give an overview of measurement and modeling techniques and results for stacked and MCM structures, describe our present measurement results together with our structure function based methodology of validating the detailed model of the package being studied. Also, we show how to derive junction-to-pin thermal resistances with a technique using structure functions.