Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}}

TL;DR

This paper introduces a new FPGA-based multiplication structure for finite fields F_{3^97} and F_{3^{6*97}}, utilizing digit-level LFSR multipliers with Karatsuba optimization, improving efficiency for cryptographic applications.

Contribution

The work presents a novel digit-level LFSR multiplier structure with Karatsuba reduction for F_{3^97} and new formulas for F_{3^{6*97}} that decrease multiplications needed, enhancing cryptographic field operations.

Findings

Reduced area of digit-multipliers using Karatsuba method.

Decreased F_{3^{6*97}} multiplications from 18 to 15.

Improved efficiency for pairing-based cryptography.

Abstract

In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works in the literature for F_{3^97}. We also propose new formulas for multiplication in F_{3^{6*97}}. These new formulas reduce the number of F_{3^97}-multiplications from 18 to 15. The fields F_{3^{97}} and F_{3^{6*97}} are relevant in the context of pairing-based cryptography.